The present invention relates to a semiconductor device having a vertical gate transistor and a method for forming the same.
For the past several decades, the semiconductor device has sustained astonishing advances and development. Every two years the size of the Metal-Oxide-Semiconductor (MOS) transistor has been reduced by a factor of two. The gate length (or gate size) has been one of the most important parameters for the semiconductor device scaling. Smaller gate lengths allow for higher packing density and faster circuits. This performance headroom also allows operation at lower voltages. This continued scaling of the transistor has made possible the explosive growth in information technology in the recent years.
At present, semiconductor devices having a physical gate length of 20 nm regime are being made. It is expected that the gate length will be reduced further and will approach 10 nm in the coming years. This scaling based simply on the reduced feature sizes, however, cannot continue forever.
DRAM industry, due to its need for high density chips, has taken a lead in the scaling of gate length. Since the size reduction in the planar direction is nearing its physical limitation, DRAM manufacturers are currently examining device scaling in the vertical direction. An example of vertical gate transistors being developed is vertical surrounding gate transistors (VSGT). VSGTs are typically metal-oxide-semiconductor field effect transistors (MOSFET) that have semiconductor pillars. The source, the drain, and the channel are defined in the pillar along a vertical direction. The gate wraps around the channel region of the pillar, and thus the name, “vertical surrounding gate transistor.”
Among other benefits, vertical gate transistors make possible the use of much smaller memory cell designs of 4F2 (i.e., the cell is 2F×2F) compared to the current memory cell designs of 8F2 or 6F2. The term “F” refers to the minimum feature size for a given semiconductor device. The vertical transistor technology's compact cell design enables highly densely-packed semiconductor devices to be realized. However, introducing the vertical transistor technology into mass manufacturing may require resolving a number of issues. One of these issues is keeping the word line resistance relatively low even as the gates are made thinner in order to accommodate the cell size reduction.